This invention relates generally to the processing of semiconductor substrates and material layers on semiconductor substrates in the fabrication of integrated circuit and other semiconductor devices, and more particularly the invention relates to masks for masking such substrates and layers for selective chemical processing.
Photoresist masking has long been employed in the fabrication of integrated circuits prior to chemical etching and dopant diffusion steps. Typically, a layer of energy sensitive resist is coated onto a substrate or another layer to be selectively chemically processed. An image of a pattern is formed in the photoresist by irradiation of the resist through an optical mask or reticle, and the developed photoresist is removed. The selectively masked substrate or layer can then be etched, by wet or dry (plasma) etch, or dopants can be introduced through the opening in the mask into the substrate or layer by diffusion or ion implantation.
With increasing densities of components in integrated circuits and the reduction of circuit dimensions into the sub-micron range, the thickness of the photoresist layer has been reduced to control pattern resolution. However, with deep sub-micron dimensions, the photoresist has become insufficient to mask underlying materials against chemical etchant.
In order to minimize the erosion of the thin resist during an etching process of underlying material layers, an intermediate layer (typically an oxide layer) is needed between the resist and the underlying material stack. Deep ultraviolet (DUV) imaging has also complicated the stack further by requiring incorporation of an anti-reflective coating (ARC). For deep and narrow features such as high aspect ratio contact (HARC) holes, a several thousand angstrom thick amorphous carbon layer is now routinely used in order to provide the selectivity required during the long (several minutes) etch process. Therefore, conventional multi-layer-resist (MLR) consists of a resist, an ARC layer, an intermediate layer (termed a hard mask) such as silicon oxynitride (SiON), and an amorphous carbon hard mask in the case of a HARC application on top of an underlying material layer.
More recently, it has become possible to eliminate the intermediate layer as well as the anti-reflective coating. The incorporation of silicon in the resist (SiPR) provides a means to generate silicon oxide on the outer surface of the resist, which then acts as a hard mask. The amorphous carbon layer (ACL) hard mask is currently deposited via a chemical vapor deposition (CVD) process, but a spin-on carbon (SOC) containing hard mask has also been introduced recently, which has superior optical properties and is more cost-effective than the ACL hard mask. Spin-on carbon is available from JSR Corporation of Japan.
Some drawbacks exist for the above bi-layer resist structure. In a conventional MLR stack, the intermediate layer (SiON) plays an important role other than as a hard mask, and this is to reduce the critical dimension (CD) defined by the resist patterning. Advances in both the resist pattern techniques and further CD reduction in the SiON layer have so far provided the required CD of the complicated features in current IC devices. As a result of the absence of the SiON layer, the CD reduction in a bi-layer mask described above now must be achieved during the pattern transfer to the carbon hard mask using plasma etching. A further problem is encountered with the silicon containing photoresist which is easily damaged by high-bias (high power at low RF frequencies) plasma etching, leading to serious micro-pitting in the bi-layer mask.